The present invention relates to an operational amplifier circuit.
An operational amplifier circuit is often used as a basic operation circuit in a semiconductor integrated circuit device. There is a demand for further improvement in various properties of the basic operation circuit due to the higher integration and lower power consumption of semiconductor integrated circuit devices.
Japanese Laid-Open Patent Publication No. 9-219636 discloses one example of an operational amplifier circuit. This conventional operational amplifier circuit will be described with reference to FIG. 1.
The operational amplifier circuit 10 includes a constant current source 11, a current mirror circuit 12, a differential input circuit 20, and an output stage circuit 30. The constant current source 11 supplies constant current I1 to the current mirror circuit 12. The current mirror circuit 12 includes N-channel MOS transistors N1 and N2. The drain of the transistor N1 is connected to the constant current source 11. The sources of the transistors N1 and N2 are connected to a low potential power supply VS. The drain of the transistor N1 is connected to the gates of the transistors N1 and N2, and the drain of the transistor N2 is connected to the differential input circuit 20.
The differential input circuit 20 includes a differential pair 21 and a current mirror circuit 22. The differential pair 21 includes N-channel MOS transistors N3 and N4. A connection node between the sources of the two transistors N3 and N4 is connected to the drain of the transistor N2. The drains of the transistors N3 and N4 are respectively connected to the drains of P-channel MOS transistors P1 and P2 configuring the current mirror circuit 22. The sources of the transistors P1 and P2 are connected to a high potential power supply VD, and the drain of the transistor P2 is connected to the gates of the transistors P1 and P2.
The gates of the transistors N3 and N4 configuring the differential pair 21 are respectively connected to first and second input terminals T1 and T2 and receive first and second input signals IP and IM, respectively. Therefore, the differential input circuit 20, which is operated based on the bias current I2 supplied from the transistor N2, changes the potential V1 at node A between the transistors N3 and P1 and the potential V2 at node B between the transistors N4 and P2 in a complementary manner by having current flow in accordance with the potential difference between the first and second input signals IP and IM.
The nodes A and B of the differential input circuit 20 are connected to the output stage circuit 30.
The output stage circuit 30 includes P-channel MOS transistors P3 and P4 and a current mirror circuit 31. The current mirror circuit 31 includes N-channel MOS transistors N5 and N6. The gates of the transistors P3 and P4 are connected to the nodes B and A, respectively. Further, the node B is connected to the drain and the gate of the transistor P2. Therefore, the transistor P3 and the transistor P2 operate as a current mirror.
The source of the transistor P3 is connected to the high potential power supply VD, and the drain is connected to the drain of the transistor N5. The transistor P4, which functions as a former transistor of a final output stage, has a source is connected to the high potential power supply VD and a drain connected to an output terminal To. Therefore, drain current I6 corresponding to the gate voltage of the transistor P4 is supplied to the output terminal To.
The transistor N5 has the same element size as the transistor N1 of the current mirror circuit 12. Further, the transistor N5 has a source connected to the low potential power supply VS and a drain connected to the transistor P3 and the gates of the two transistors N5 and N6. The transistor N6 functions as a latter transistor in the final output stage. The transistor N6 has a source connected to the low potential power supply VS and a drain connected to the output terminal To. The drain voltages of the two transistors P4 and N6 are output from the output terminal To as an output signal Vout. The transistor N6 draws in drain current I7 corresponding to the element size ratio of the transistor N5 and the transistor N6 from the output terminal To.
The operational amplifier circuit 10 receives the output signal Vout as the second input signal IM. That is, the second input terminal T2 is connected to the output terminal To, and the operational amplifier circuit 10 operates as a voltage follower. The first input signal IP and the second input signal IM thus become equal when the gate voltage of the transistor P3 and the gate voltage of the output transistor P4 are the same, that is, when the same current is output to the nodes A and B of the current mirror circuit 22 configured by the transistors P1 and P2.